[linux] makefile Rules

Makefile chứa các rules có định dạng như sau:

Đích ... : Điều kiện tiên quyết ...
             Lệnh
             ...
             ...

Đích là các file thực thi hoặc file objects.

Điều kiện tiên quyết là các file đầu vào để biên dịch mà file Đích phụ thuộc vào.

Lệnh là để thực thi sự biên dịch.

     edit : main.o kbd.o command.o display.o \
            insert.o search.o files.o utils.o
             cc -o edit main.o kbd.o command.o display.o \
                        insert.o search.o files.o utils.o

     main.o : main.c defs.h
             cc -c main.c
     kbd.o : kbd.c defs.h command.h
             cc -c kbd.c
     command.o : command.c defs.h command.h
             cc -c command.c
     display.o : display.c defs.h buffer.h
             cc -c display.c
     insert.o : insert.c defs.h buffer.h
             cc -c insert.c
     search.o : search.c defs.h buffer.h
             cc -c search.c
     files.o : files.c defs.h buffer.h command.h
             cc -c files.c
     utils.o : utils.c defs.h
             cc -c utils.c
     clean :
             rm edit main.o kbd.o command.o display.o \
                insert.o search.o files.o utils.o

[linux] Predefined rules trong makefile

Chương trình ban đầu

OBJECTS = data.o main.o io.o
project1: $(OBJECTS)
        cc $(OBJECTS) -o project1
data.o: data.c data.h
        cc -c data.c
main.o: data.h io.h main.c
        cc -c main.c
io.o: io.h io.c
        cc -c io.c

Predefined rules

By itself, make knows already that in order to create a .o file, it must use cc -c on the corresponding .c file. These rules are built into make, and you can take advantage of this to shorten your Makefile. If you just indicate just the .h files in the dependency line of the Makefile that the current target is dependent on, make will know that the corresponding .c file is already required. You don’t even need to include the command for the compiler.

This reduces our Makefile further, as shown:

OBJECTS = data.o main.o io.o
project1: $(OBJECTS)
        cc $(OBJECTS) -o project1
data.o: data.h
main.o: data.h io.h
io.o: io.h

One thing to consider, however, is that when you are compiling programs on Wiliki, you may wish to add a CFLAGS macro at the top of your Makefile to enable the compiler to use ANSI standard C compilation. The macro looks like this:
CFLAGS=-Aa -D_HPUX_SOURCE
This will allow make to use ANSI C with the predefined rules.

[linux] Some Makefile Macros

Special macros

In addition to those macros which you can create yourself, there are a few macros which are used internally by the make program. Here are some of those, listed below:

CC

Contains the current C compiler. Defaults to cc.

CFLAGS

Special options which are added to the built-in C rule. (See next page.)

$@

Full name of the current target.

$?

A list of files for current dependency which are out-of-date.

$<

The source file of the current (single) dependency.

You can also manipulate the way these macros are evaluated, as follows, assuming that OBJS = data.o io.o main.o, using $(OBJS:.o=.c) within the Makefile substitutes .o at the end with .c, giving you the following result: data.c io.c main.c